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EL5172, EL5372
Data Sheet January 25, 2008 FN7311.8
250MHz Differential Line Receivers
The EL5172 and EL5372 are single and triple high bandwidth amplifiers designed to extract the difference signal from noisy environments. They are primarily targeted for applications such as receiving signals from twisted-pair lines or any application where common mode noise injection is likely to occur. The EL5172 and EL5372 are stable for a gain of one and requires two external resistors to set the voltage gain. The output common mode level is set by the reference pin (VREF), which has a -3dB bandwidth of over 120MHz. Generally, this pin is grounded but it can be tied to any voltage reference. The output can deliver a maximum of 60mA and is short circuit protected to withstand a temporary overload condition. The EL5172 is available in the 8 Ld SOIC and 8 Ld MSOP packages and the EL5372 in a 24 Ld QSOP package. Both are specified for operation over the full -40C to +85C temperature range.
Features
* Differential input range 2.3V * 250MHz 3dB bandwidth * 800V/s slew rate * 60mA maximum output current * Single 5V or dual 5V supplies * Low power - 5mA to 6mA per channel * Pb-free available (RoHS compliant)
Applications
* Twisted-pair receivers * Differential line receivers * VGA over twisted-pair * ADSL/HDSL receivers * Differential to single-ended amplification * Reception of analog signals in a noisy environment
Pinouts
EL5172 (8 LD SOIC, MSOP) TOP VIEW
FB 1 IN+ 2 IN- 3 REF 4 + 8 OUT 7 VS6 VS+ 5 EN REF1 1 INP1 2 INN1 3 NC 4 REF2 5 INP2 6 INN2 7 NC 8 REF3 9 INP3 10 INN3 11 NC 12 + + + -
EL5372 (24 LD QSOP) TOP VIEW
24 NC 23 FB1 22 OUT1 21 NC 20 VSP 19 VSN 18 NC 17 FB2 16 OUT2 15 EN 14 FB3 13 OUT3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2005, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL5172, EL5372 Ordering Information
PART NUMBER EL5172IS EL5172IS-T7* EL5172IS-T13* EL5172ISZ (Note) EL5172ISZ-T7* (Note) EL5172ISZ-T13* (Note) EL5172IY EL5172IY-T7* EL5172IY-T13* EL5172IYZ (Note) EL5172IYZ-T7* (Note) EL5172IYZ-T13* (Note) EL5372IU EL5372IU-T7* EL5372IU-T13* EL5372IUZ (Note) EL5372IUZ-T7* (Note) EL5372IUZ-T13* (Note) 5172IS 5172IS 5172IS 5172ISZ 5172ISZ 5172ISZ h h h BAAWA BAAWA BAAWA EL5372IU EL5372IU EL5372IU EL5372IUZ EL5372IUZ EL5372IUZ PART MARKING PACKAGE 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) (Pb-free) 24 Ld QSOP (150 mil) 24 Ld QSOP (150 mil) 24 Ld QSOP (150 mil) 24 Ld QSOP (150 mil) (Pb-free) 24 Ld QSOP (150 mil) (Pb-free) 24 Ld QSOP (150 mil) (Pb-free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7311.8 January 25, 2008
EL5172, EL5372
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
Thermal Information
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW -3dB Bandwidth
VS+ = +5V, VS- = -5V, TA = +25C, VIN = 0V, RL = 500, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
AV =1, CL = 2.7pF AV =2, RF = 1000, CL = 2.7pF AV =10, RF = 1000, CL = 2.7pF
250 70 10 25 550 550 800 700 10 20 100 1000 1000
MHz MHz MHz MHz V/s V/s ns ns MHz MHz V/s nV/Hz pA/Hz dBc dBc dBc dBc % dB
BW SR
0.1dB Bandwidth Slew Rate
AV =1, CL = 2.7pF VOUT = 3VP-P, 20% to 80%, EL5172 VOUT = 3VP-P, 20% to 80%, EL5372
tSTL tOVR GBWP
Settling Time to 0.1% Output Overdrive Recovery Time Gain Bandwidth Product
VOUT = 2VP-P
VREFBW (-3dB) VREF -3dB Bandwidth VREFSR VN IN HD2 VREF Slew Rate Input Voltage Noise Input Current Noise Second Harmonic Distortion
AV =1, CL = 2.7pF VOUT = 2VP-P, 20% to 80% at f = 11kHz at f = 11kHz VOUT = 1VP-P, 5MHz VOUT = 2VP-P, 50MHz
120 600 26 2 -66 -63 -84 -76 0.04 0.41 90
HD3
Third Harmonic Distortion
VOUT = 1VP-P, 5MHz VOUT = 2VP-P, 50MHz
dG d eS
Differential Gain at 3.58MHz Differential Phase at 3.58MHz Channel Separation at 100kHz
RL = 150, AV = 2 RL = 150, AV = 2 EL5372 only
INPUT CHARACTERISTICS VOS IIN RIN CIN DMIR CMIR+ CMIRVREFIN+ VREFINInput Referred Offset Voltage Input Bias Current (VIN, VINB, VREF) Differential Input Resistance Differential Input Capacitance Differential Input Range Common Mode Positive Input Range at VIN+, VINCommon Mode Positive Input Range at VIN+, VINReference Input Positive Voltage Range Reference Input Negative Voltage Range VIN+ = VIN- = 0V VIN+ = VIN- = 0V 3.3 2.1 3.3 -14 7 -6 300 1 2.38 3.5 -4.5 3.7 -3.9 -3.6 -4.3 V 2.5 25 -3 mV A k pF V V
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FN7311.8 January 25, 2008
EL5172, EL5372
Electrical Specifications
PARAMETER CMRR Gain VS+ = +5V, VS- = -5V, TA = +25C, VIN = 0V, RL = 500, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise Specified. (Continued) DESCRIPTION Input Common Mode Rejection Ratio Gain Accuracy CONDITIONS VIN = 2.5V VIN = 1 MIN 75 0.985 TYP 95 1 1.015 MAX UNIT dB V
OUTPUT CHARACTERISTICS VOUT Positive Output Voltage Swing Negative Output Voltage Swing IOUT(Max) ROUT SUPPLY VSUPPLY IS (on) IS (off)+ Supply Operating Range Power Supply Current Per Channel - Enabled Positive Power Supply Current - Disabled EN pin tied to 4.8V, EL5172 EN pin tied to 4.8V, EL5372 IS (off)PSRR ENABLE tEN tDS VIH VIL IIH-EN IIL-EN Enable Time Disable Time EN Pin Voltage for Power-up EN Pin Voltage for Shut-down EN Pin Input Current High Per Channel EN Pin Input Current Low Per Channel At VEN = 5V At VEN = 0V -10 VS+ - 0.5 40 -3 60 150 1.4 VS+ - 1.5 ns s V V A A Negative Power Supply Current - Disabled Power Supply Rejection Ratio VS from 4.5V to 5.5V -150 50 VS+ to VS4.75 4.6 5.6 80 1.7 -120 58 11 7 100 5 -90 V mA A A A dB Maximum Output Current Output Impedance RL = 500 to GND RL = 500 to GND RL = 10 60 3.3 3.63 -3.87 95 100 -3.5 V V mA m
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FN7311.8 January 25, 2008
EL5172, EL5372 Pin Descriptions
EL5172 1 2 3 4 5 6 7 8 1, 5, 9 2, 6, 10 3, 7, 11 4, 8, 12, 18, 21, 24 13, 16, 22 14, 17, 23 15 19 20 EL5372 PIN NAME FB IN+ INREF EN VS+ VSOUT REF1, 2, 3 INP1, 2, 3 INN1, 2, 3 NC OUT1, 2, 3 FB1, 2, 3 EN VSN VSP Feedback input Non-inverting input Inverting input Sets the common mode output voltage level Enabled when this pin is floating or the applied voltage VS+ - 1.5 Positive supply voltage Negative supply voltage Output voltage Reference input, controls common-mode output voltage Non-inverting inputs Inverting inputs No connect; grounded for best crosstalk performance Non-inverting outputs Feedback from outputs Enabled when this pin is floating or the applied voltage VS+ - 1.5 Negative supply Positive supply PIN FUNCTION
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FN7311.8 January 25, 2008
Connection Diagrams
RG
RF = 0 -5V 1 FB INP 2 INP 3 INN 4 REF RS2 50 RS2 50 RS3 50 EL5172 OUT 8 VSN 7 VSP 6 EN 5 +5V EN CL 2.7pF VOUT RL 500
6
REF1 INP1 INN1 REF2 INP2 INN2 REF3 INP3 INN3 RSP1 50 RSN1 50 RSR1 50 RSP2 50 RSN2 50 RSR2 50
FN7311.8 January 25, 2008
INN REF
EL5172, EL5372
RG 1 REF1 2 INP1 3 INN1 4 NC 5 REF2 6 INP2 7 INN2 8 NC 9 REF3 10 INP3 11 INN3 RSP3 50 RSN3 50 RSR3 50 12 NC NC 24 RF FB1 23 OUT1 22 NC 21 VSP 20 VSN 19 NC 18 FB2 17 OUT2 16 EN 15 FB3 14 OUT3 13 EL5372 RG RF RG RF
+5V
OUT1 CL1 2.7pF RL1 500
OUT2 RL2 500
OUT3 -5V CL2 2.7pF CL3 2.7pF RL3 500
ENABLE
EL5172, EL5372 Typical Performance Curves
AV = 1, RL = 500, CL = 2.7pF 4 3 2 MAGNITUDE (dB) MAGNITUDE (dB) 1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G VS = 2.5V VS = 5V 4 3 2 1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G VS = 2.5V VS = 5V AV = 1, RL = 100, CL = 2.7pF
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
VS = 5V, RL = 500, CL = 2.7pF 4 3 NORMALIZED GAIN (dB) 2
FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
VS = 5V, AV = 1, RL = 500 5 4 3 MAGNITUDE (dB) 2 1 0 -1 -2 -3 -4 CL = 10pF CL = 2.7pF CL = 15pF CL = 56pF CL = 33pF
1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G AV = 10 AV = 2 AV = 5 AV = 1
-5 1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE vs VARIOUS GAIN
FIGURE 4. FREQUENCY RESPONSE vs CL
VS = 5V, AV = 1, RL = 500 5 4 3 MAGNITUDE (dB) 2 1 0 -1 -2 -3 -4 -5 1M 10M 100M 1G CL = 10pF CL = 2.7pF CL = 15pF CL = 56pF NORMALIZED GAIN (dB) CL = 33pF 4 3 2 1 0 -1 -2 -3 -4 -5
VS = 5V, AV = 2, RL = 500, CL = 2.7pF
RF = 1k RF = 500 RF = 200
-6 1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE vs CL
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS RF
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FN7311.8 January 25, 2008
EL5172, EL5372 Typical Performance Curves
4 3 NORMINALIZED GAIN (dB) 2 1 GAIN (dB) 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G VS = 2.5V VS = 5V AV = 1, RL = 500, CL = 2.7pF 60 50 40 30 20 10 0 -10 -20 -30 -40 10k 100k 1M 10M 100M 270 225 180 135 45 0 -45 -90 -135 -180 500M PHASE () 90
(Continued)
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE FOR VREF
FIGURE 8. OPEN LOOP GAIN
100
0 -10
IMPEDENCE ()
-20 10 PSRR (dB) -30 -40 -50 -60 -70 -80 0.1 10k 100k 1M FREQUENCY (Hz) 10M 100M -90 1k 10k PSRR100k 1M 10M 100M PSRR+
1
FREQUENCY (Hz)
FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 10. PSRR vs FREQUENCY
100 90 80 70 CMRR (dB) 60 50 40 30 20 10 0 100k 1M 10M FREQUENCY (Hz) 100M 1G VOLTAGE NOISE (nV/Hz) CURRENT NOISE (pA/Hz)
1k
100 EN 10 IN 1 10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 11. CMRR vs FREQUENCY
FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY
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FN7311.8 January 25, 2008
EL5172, EL5372 Typical Performance Curves
0 -10 -20 DISTORTION (dB) -30 GAIN (dB) -40 -50 -60 -70 -80 -90 -100 100k 1M 10M FREQUENCY (Hz) 100M 1G CH1 <=> CH3 CH1 <=> CH2, CH2 <=> CH3
(Continued)
VS = 5V, RL = 500, f = 5MHz
-45 -50 -55 -60 -65 -70 -75 -80 -85
HD2
(AV
= 2)
(AV HD2
= 1)
HD3 (A V = 2)
HD3 (AV = 1)
1
2
3
4 VOP-P (V)
5
6
7
FIGURE 13. CHANNEL ISOLATION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE
-45 -50 -55 DISTORTION (dB) -60 -65 -70 -75 -80 -85
VS = 5V, f = 5MHz, VOP-P = 1V @AV = 1, VOP-P = 2V @AV = 2
HD 3 (A
-40 -50 DISTORTION (dB)
VS = 5V, RL = 500, VOP-P = 1V FOR AV = 1, VOP-P = 2V for AV = 2
HD2 (AV = 2)
V =2 )
HD2 (A V = 2)
-60 -70 -80 -90 -100
HD2 (A V = 1)
HD3 (AV
= 2)
HD2 (AV = 1)
HD3 (AV = 1)
HD3 (AV = 1) 200 300 400 500 600 700 800 900 1000
-80 100
0
5
10
15
20
25
30
35
40
RLOAD ()
FREQUENCY (MHz)
FIGURE 15. HARMONIC DISTORTION vs LOAD RESISTANCE
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
50mV/DIV
0.5V/DIV
10ns/DIV
10ns/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
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FN7311.8 January 25, 2008
EL5172, EL5372 Typical Performance Curves
(Continued)
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
M = 100ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
CH1
CH1
CH2 CH2
100ns/DIV
400ns/DIV
FIGURE 19. ENABLED RESPONSE
FIGURE 20. DISABLED RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 POWER DISSIPATION (W) 1.0 0.8 625mW 0.6 0.4 486mW 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) MSOP8 JA = +206C/W SOIC8 JA = +160C/W POWER DISSIPATION (W) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.136W 909mW 870mW QSOP24 JA = +88C/W SOIC8 JA = +110C/W
870mW QSOP24 JA = +115C/W
MSOP8/10 JA = +115C/W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Simplified Schematic
VS+ I1 I2 RD1 I3 I4 RD2 R3 R4
Q8 VIN+ Q1 VINQ2 FBP Q3 FBN Q4 Q7
VB1
Q9 x1 25 Q6 VB2 CC R1 R2 VSVOUT
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FN7311.8 January 25, 2008
EL5172, EL5372 Description of Operation and Application Information
Product Description
The EL5172 and EL5372 are wide bandwidth, low power and single/differential ended to single ended output amplifiers. The EL5172 is a single channel differential to single ended amplifier. The EL5372 is a triple channel differential to single ended amplifier. The EL5172 and EL5372 are internally compensated for closed loop gain of +1 or greater. Connected in gain of 1 and driving a 500 load, the EL5172 and EL5372 have a -3dB bandwidth of 250MHz. Driving a 150 load at gain of 2, the bandwidth is about 50MHz. The bandwidth at the REF input is about 450MHz. The EL5172 and EL5372 are available with a power-down feature to reduce the power while the amplifier is disabled.
Choice of Feedback Resistor and Gain Bandwidth Product
For applications that require a gain of +1, no feedback resistor is required. Just short the OUT pin to the FB pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL5172 and EL5372 depends on the load and the feedback network. RF and RG appear in parallel with the load for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum bandwidth performance. For a gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 500 to 1k. For AV = 2 and RF = RG = 1k, the BW is about 80MHz and the frequency response is very flat. The EL5172 and EL5372 have a gain bandwidth product of 100MHz. For gains 5, its bandwidth can be predicted by Equation 1:
Gain x BW = 100MHz (EQ. 1)
Input, Output and Supply Voltage Range
The EL5172 and EL5372 have been designed to operate with a single supply voltage of 5V to 10V or a split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.3V to 3.3V for 5V supply. The differential mode input range (DMIR) between the two inputs is about from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.6V to 3.3V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal to be distorted. The output of the EL5172 and EL5372 can swing from -3.8V to 3.6V at 500 load at 5V supply. As the load resistance becomes lower, the output swing is reduced respectively.
Driving Capacitive Loads and Cables
The EL5172 and EL5372 can drive 56pF capacitance in parallel with 500 load to ground with 4dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking.
Over All Gain Settings
The gain setting for the EL5172 and the EL5372 is similar to the conventional operational amplifier. The output voltage is equal to the difference of the inputs plus VREF and then times the gain.
RF V O = ( V IN + - V IN - + V REF ) x 1 + ------- R G
EN VIN+ VIN+ VREF FB + RF RG G/B VO
Disable/Power-Down
The EL5172 and EL5372 can be disabled and its outputs placed in a high impedance state. The turn-off time is about 1.4s and the turn-on time is about 150ns. When disabled, the amplifier's supply current is reduced to 80A for IS+ and
FIGURE 23.
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FN7311.8 January 25, 2008
EL5172, EL5372
120A for IS- typically, thereby effectively eliminating the power consumption. The amplifier's power-down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above VS+ - 0.5V. If a TTL signal is used to control the enabled/disabled function, Figure 24 could be used to convert the TTL signal to CMOS signal.
5V
For sourcing, use Equation 3:
V OUT PD MAX = V S x I SMAX + ( V S + - V OUT ) x ------------------- x i R
LOAD
(EQ. 3)
For sinking, use Equation 4:
PD MAX = [ V S x I SMAX + ( V OUT - V S - ) x I LOAD ] x i (EQ. 4)
Where: * VS = Total supply voltage
EN
10k 1k CMOS/TTL
* ISMAX = Maximum quiescent supply current per channel * VOUT = Maximum output voltage of the application * RLOAD = Load resistance * ILOAD = Load current
FIGURE 24.
* i = Number of channels By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat.
Output Drive Capability
The EL5172 and EL5372 have internal short circuit protection. Its typical short circuit current is 95mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds 60mA. This limit is set by the design of the internal metal interconnections.
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces.
Power Dissipation
With the high output drive capability of the EL5172 and EL5372, it is possible to exceed the +135C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 2:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA (EQ. 2)
* TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package Assuming the REF pin is tied to GND for VS = 5V application, the maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
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FN7311.8 January 25, 2008
EL5172, EL5372
Typical Applications
0
50 EL5173, EL5373 OR EL5172, EL5372 50
VFB VIN EL5172, EL5372
VOUT
50 ZO = 100 50
VINB VREF
FIGURE 25. TWISTED PAIR CABLE RECEIVER
As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate for this loss is to boost the high frequency gain at the receiver side.
R3 C1
R1
R2
GAIN (dB) 1 + R2/R1
VFB 50 VIN VINB ZO = 100 50 VREF fA fC f EL5172, EL5372 VOUT 1 + R2/(R1 + R3)
FIGURE 26. COMPENSATED LINE RECEIVER
Level Shifter and Signal Summer
The EL5172 and EL5372 contains two pairs of differential pair input stages, which make sure that the inputs are all high impedance inputs. To take advantage of the two high impedance inputs, the EL5172 and EL5372 can be used as a signal summer to add two signals together. One signal can be applied to VIN+, the second signal can be applied to REF and VIN- is ground. The output is equal to Equation 5:
V O = ( V IN + + V REF ) x Gain (EQ. 5)
Also, the EL5172 and EL5372 can be used as a level shifter by applying a level control signal to the REF input.
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FN7311.8 January 25, 2008
EL5172, EL5372 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL Ao
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4o
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
14
FN7311.8 January 25, 2008
EL5172, EL5372 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 4o DETAIL X
A1
15
FN7311.8 January 25, 2008
EL5172, EL5372 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
E
E1
PIN #1 I.D.
A2 b c
B
1 (N/2)
D E E1
e C SEATING PLANE 0.10 C N LEADS b
H
e L L1 N
0.08 M C A B
L1 A c SEE DETAIL "X"
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3o
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN7311.8 January 25, 2008

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